
77
8008H–AVR–04/11
ATtiny48/88
10.4
Register Description
10.4.1
MCUCR – MCU Control Register
Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
“Con-10.4.2
PORTCR – Port Control Register
Bits 7:4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise Break-Before-Make mode is activated. The
intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further
Bits 3:0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled
even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn}
= 0b01). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD)
Table 10-13. Overriding Signals for Alternate Functions in PD[3:0]
Signal
Name
PD3/INT1/PCINT19
PD2/INT0/PCINT18
PD1/PCINT17
PD0/PCINT16
PUOE
0
000
PUO
0
000
DDOE
0
DDOV
0
PVOE
0
000
PVOV
0
000
DIEOE
INT1 ENABLE +
PCINT19 PCIE2
INT0 ENABLE +
PCINT18 PCIE1
PCINT17 PCIE2
PCINT16 PCIE2
DIEOV
1
111
DI
PCINT19 INPUT
INT1 INPUT
PCINT18 INPUT
INT0 INPUT
PCINT17 INPUT
PCINT16 INPUT
AIO
–
–––
Bit
7
6
5
4
3
2
1
0
–
BPDS
BPDSE
PUD
–
MCUCR
Read/Write
R
R/W
R
Initial Value
0
Bit
7
6
5
4
3
2
1
0
BBMD
BBMC
BBMB
BBMA
PUDD
PUDC
PUDB
PUDA
PORTCR
Read/Write
R/W
Initial Value
0